Scalable Multi-Stage CMOS OTAs With a Wide CL-Drivability Range Using Low-Frequency Zeros

This work introduces a multi-stage CMOS OTA design technique that allows cascading identical gain stages (for arbitrarily scalable high DC gain) while driving an ultra-wide range of capacitive loads (
$\text{C}_{\text {L}}\text{s}$
). At the heart of the proposed design is a new frequency compensation technique (FCT) that relies on low-frequency left-half-plane zeros to allow the proposed OTA to operate for a desired closed-loop behavior. In this work, classical gain-stages (i.e., differential pair and common source transistors) are used to design fully-differential 2-, 3-, 4- and 5-stage CMOS OTAs. The proposed 2-to-4-stage designs have been fabricated in TSMC 65 nm CMOS process and the measurement results show that the 2-stage OTA is achieving a DC gain of 50 dB with a
$\text{C}_{\text {L}}$
-drivability ratio (i.e.,
$\text{C}_{\text {L,max}}/\text{C}_{\text {L,min}}$
) of
$10,000\times $
, the 3-stage OTA is achieving a DC gain of 70 dB with a
$\text{C}_{\text {L}}$
-drivability of
$1,000,000\times $
, and the 4-stage OTA is achieving a DC gain of 90 dB with a
$\text{C}_{\text {L}}$
-drivability of
$1,000,000\times $
. This is a 10-to-1000-time improvement in the state-of-the-art, as the highest
$\text{C}_{\text {L}}$
-drivability reported to date is
$1000\times $
. Accordingly, the proposed OTAs can cover a wider range of applications than any other reported works.