Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique

This paper presents a CDR circuit with wide lock-in range and low jitter. By using the Frequency Increase/Decrease Control circuit and the Modified DQFD (Digital Quadricorrelator Frequency Detector), the lock-in range is enhanced. Besides, the problem of the state loss at wide frequency range detection is avoided. The Coarse-fine Tuning VCO provides two control wires such that separate loop filters could be involved in the dual loops. Thus, the noise and jitter could be further miniaturized. The proposed design is implemented with a typical 40 nm CMOS process. The simulated lock-in range is 1-6.5 GHz and the simulated RMS jitter is 5.79 ps.