Adaptive biasing of a 5.8 GHz CMOS oscillator

A key concept for VCOs in next-generation RF links is to allow phase noise performance to be scaled back to save power in times of reduced demand. A 5.8 GHz VCO and biasing circuitry in a 0.5 μm CMOS process have a performance adjustable from -107 dBc/Hz (1 MHz offset) with 6.2 mW dissipated to -121 dBc/Hz using 70 mW.