Design of High Speed 9T SRAM Cell at 16 nm Technology with Simultaneous Read-Write Feature

This study presents a new 9 transistor (9T) static random access memory (SRAM) architecture with effortless and stable read operation. The proposed topology is implemented in predictive technology model (PTM) 16nm technology using LTspice software. Delay and power consumption of read and write operations, and power delay product (PDP) have been investigated and compared to traditional 6T, 8T, 9T, and 10T SRAM cells. The simulation results demonstrate that the proposed design provides fastest read operation and optimized overall PDP. The noise margin is also improved compared to existing 6T and 9T topologies.