A 600 MHz VLIW DSP

A 600 MHz VLIW DSP, which implements the C64x VelociTI.2/spl trade/ architecture delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates at 0.3 mW/MMAC (16 b). The chip has 64 M transistors and dissipates 718 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHz and 0.9 V. It has an 8-way VLIW DSP core, a 2-level memory system, and 2.4 GB/s I/O bandwidth. The DSP chip is implemented in 0.13 μm CMOS technology with 6-layer copper metalization.