Hysteresis Associated with Intrinsic-Oxide Traps in Gate-Tunable Tetrahedral CVD-MoS2 Memristor

We introduce back gated memristor based on CVD-grown 30–40 nm thick MoS
2
channel. The device demonstrates bipolar behaviour and the measurements are consistent with the simulations performed within the intrinsic-oxide traps model. This confirms the theory that the source of hysteresis in thin-film MoS
2
memristors is charge trapping on MoS
2
/SiO
2
interface and the grain boundaries. The impact of back gate voltage bias, voltage sweep range and channel area on memristive effect was studied and quantified using hysteresis area. Hysteresis in bipolar memristors can be tuned by back gate voltage, which makes these devices promising for neuromorphic computing.