Is ESD Protection Design Planning for Large SoC Verified During SoC Floorplan Design Stage?

Flawless design planning for ESD protection on large SoCs which needs to be intercepted during the floorplan stage of the SoC design cycle is getting important. Shortfall to integrate any essential protection and detecting such flaws during ESD signoff verification at a later stage of the SoC design cycle could lead to impactful last-minute SoC floorplan change, resulting in product time-to-market delays