ESD Protection Based on Stacked SCRs With Adjustable Triggering Voltage for CMOS High-Voltage Application

This paper presents a new local ESD protection structure for High Voltage Application. This structure is based on a stack of Bi-directional SCRs and realized in 55nm CMOS technology node. A specific isolation has been studied to sustain 35V, but it also determines the Voltage Triggering of the protection.