On the Design of Iterative Approximate Floating-Point Multipliers

Approximate multipliers provide power and area-saving for error-resilient applications. In this paper, we first propose two approximate floating-point multipliers based on two-dimensional pseudo-Booth encoding: floating-point pseudo-Booth (PB), and floating-point iterative pseudo-Booth (IPB). The accuracy of proposed multipliers can be tuned by three parameters: iteration, encoder's radix (R), and word length after truncation (W). Next, we developed the conventional iterative multipliers with a simplified steering circuit for their correction part to eliminate the power consumption of multipliers. The proposed iterative multipliers are compared with conventional iterative integer multipliers implemented by a simplified steering circuit for the floating-point area. The results reveal that the proposed PB-R4-W4 and IPB-R16-W19, compared to the exact floating-point multiplier, provide up to 98.9% and 67.5% reductions in power consumption, respectively, in TSMC 180nm CMOS technology. Also, their MRED values are, respectively, 2.9% and
$({7.4 \times {{10}}^{ - 4}})$
%. Finally, we evaluated the functionality of the proposed multipliers for real-life applications, including a hyper-plane classifier and two image processing applications of smoothing and sharpening.