An efficient image compression hardware design architecture

With the explosion of industry 4.0 technologies, digital image compression technology has gradually played an important role in the fast communication and live processing of images over the internet. As a result, the demand for storing and transferring images is increasing day by day. Image compression is an application that compresses data on digital images, the main goal is to decrease the redundancy of image data so that it can be stored or transmitted in an efficient form. This paper proposes a hardware efficient architecture of the Microshift - an image compression algorithm. In this design, the image is first micro-shifted, then the sub-quantized values are further compressed. In decompression, we use the MRF model to recover the bit-depth by exploiting the spatial correlation of natural images. Experimental results on a field-programmable gate-array (FPGA) platform illustrate that the proposed architecture enables operation around 172 MHz and the peak signal to noise ratio (PSNR) of 31.51 dB with 1.5 bits per pixel(BPP) and structural similarity index measurement(SSIM) achieve 0.9. This design is synthesized on the Altera Cyclone V- 5CSEMA5F31C8.