Characterization and Implementation of Radar System Applications on a Reconfigurable Dataflow Architecture

The fast developed and widely used radar system techniques call for novel solutions on hardware design. Under a massive data source and the real-time requirements in radar signal processing scenarios (e.g., Synthetic Aperture Radar (SAR)), reconfigurable dataflow architecture is considered as a promising solution. In this article, we first extract the typical algorithms in radar systems and characterize their dataflow manners. Then a reconfigurable dataflow architecture is proposed, with high width SIMD extended PE. The application implementations with mapping strategy and workflow are shown to reach high hardware utilization and efficient data supply. Our work achieves
$8 \times$
and
$5.3\times$
energy efficiency improvement over DSP and GPU (NVIDIA Tesla V100), respectively, on large scale FFT, as well as high performance. Under actual scene of
$8K \times 8K$
SAR imaging baseline, it gets
$9.4 \times$
speedup over a six-core CPU.