Achieving a Relative Bandwidth of 176% with a Single PLL at up to 12.5 GHz

This work presents a PLL architecture to achieve a relative bandwidth of >100% with a single PLL. To showcase the approach, a PLL generating frequencies inside the UWB is shown. The PLL utilizes the tuning range of two VCOs, while a single loop filter architecture generates both tuning voltages. To reduce implementation effort, the architecture can be simulated as a single, equivalent VCO. This equivalent VCO itself offers the maximum relative bandwidth of 200%. Additionally, it offers a more linear tuning curve than a single VCO. The maximum frequency of the PLL is 12.5 GHz, while its minimum frequency and hence relative bandwidth is only limited by the minimum divider value and reference frequency of the commercially available PLL.