Design of a Low Voltage D-band LNA in 22 nm FDSOI

This paper presents a low voltage D-band Low Noise Amplifier (LNA) manufactured in a 22 nm fully-depleted silicon-on-insulator FDSOI CMOS technology. The circuit consists of 4 differential stages. The first stage is optimized for minimal noise, while the other three are optimized to achieve maximum gain. Therefore, a capacitive neutralization technique is applied. Transmission-line-based matching networks are used to match the stages for a bandwidth of over 20 GHz. The measurement results show a gain of 17 dB while achieving a low noise figure of less than 8 dB at a supply voltage of only 0.8 V.