A 44 GHz-BW 18.5 GS/s Sampling Front-End Robust to Power Supply and Common-Mode Variations in 22 nm FDSOI

This paper presents the design and implementation of a pseudo-differential buffered front-end sampler (T&H) operating at 18.5 GS/s with 44 GHz measured signal bandwidth. The highly-linear sampler, intended for a 5-bit 4X time-interleaved (TI) 74 GS/s flash ADC, is realized in a 22 nm FD-SOI (FDX) CMOS process. It comprises an ultra-low jitter limiting clock path and a forward-body-biased source-follower based T&H architecture maximizing the overall linearity and effective sampling bandwidth, as well as achieving a differential input range of 600
$\mathbf{mV}_{\mathbf{ppd}}$
by using a dual 1.2 V and 0.9 V supply voltage. The core T&H design has been presented in [1]. The ultra-wideband T&H design is highly insensitive to both power supplies (0.9V and 1.2V), as well as input common-mode variations. The obtained measurement results confirm robustness. The nominal SFDR and SNR remains well above 37.6 dBc and 39.3 dB (ENOB=5.49 bits), respectively, using a single-tone sine wave up to 39 GHz (5th Nyquist zone). Extended two-tone linearity characterizations reveal intermodulation products IM2 and IM3 of better than 44.5 and 40.5 dBc for a HF two-tone input at
$\mathbf{f}_{\text{in1}}=35.2$
GHz and
$\mathrm{f}_{\text{in}2}=36.1$
GHz. Across
$\pm 10{\%}$
supply variations, the SNR and SFDR merely vary by 1 and 2 dB, respectively. The sensitivity to
$\pm 10{\%}$
input common-mode variations is even less than 1 dB for the same 39 GHz single-tone test. The compact differential design considering the input buffers, T&H core, clock buffer and low-jitter sample-phase occupies a core area as small as
$0.004\ \text{mm}^{2}$
in the utilized 22 nm FD-SOI process. The total power consumption is only 75mW of which 10mW is consumed by the entire clock path operating from the 0.9V supply.