An Adaptive Accelerator for Convolutional Neural Networks Using Partial Reconfiguration on FPGA

The use of FPGAs to accelerate convolutional neural networks (ConNN) has become a hot topic of research due to recent improvements in FPGA devices with respect to computing capability, power efficiency and ease of use. The majority of FPGA accelerators are designed with a fixed hardware structure in order to maximize resource utilization within the resource constraints of these devices. However, because ConNN models comprise layers with different characteristics, a specified processor architecture may provide sub-optimal performance. In order to address this problem, we propose a self-adaptive hardware accelerator which is capable of modifying its architecture while running the ConNN model. A partial reconfiguration approach is used to reconfigure the structure of the proposed accelerator on Zynq XC7Z020 during runtime. To demonstrate the effectiveness of the proposed design, an object detection method named YOLOv1-tiny is implemented. In our experiments, the proposed accelerator improves throughput and achieves higher resource efficiency compared to a static accelerator.