Implementation of Convolutional Neural Network Accelerator based on ZYNQ

As convolutional neural network (CNN) has the parallel convolutional pooling layer and a large number of convolutional multiplicative operations, it becomes a hot research topic to accelerate the forward operation of the neural network by using field programmable gate array (FPGA). This paper proposes a design and implementation method of an FPGA-based CNN accelerator. Based on the Xilinx ZYNQ, this paper selects a typical CNN model, and proposes an ARM+FPGA software-hardware collaboration scheme which is controlled by ARM and accelerated by FPGA hardware. Through the software-hardware collaboration, the scheme adopts the convolutional layer-pooling layer-convolutional layer-pooling layer four-layer pipeline architecture, as well as the model of full parallelism between convolution kernels, partial parallelism within convolution kernels and partial parallelism of the output, to accelerate the convolutional pooling operation of CNN. The experimental results show that under the operating frequency of l00Mhz, the computing performance of the CNN accelerator is 31.24 GOP/s, the power consumption is 1. 501w, and the energy efficiency ratio is 20.81GOP/(s$\cdot$W). While maintaining low energy consumption, this scheme can effectively reduce the use of on-chip resources and achieve the effect of acceleration.