Performance Limits of Gated Delay Line Time Integrators

Delta-sigma time-to-digital converters ($\triangle\Sigma$ TDCs) are known for their ability to deliver a resolution beyond th elimits of chosen technology. To realize an all-digital $\triangle\Sigma$ TDC so as to fully benefit from the merits of technology scaling, all-digital time integrators (ADTIs) are needed. The performance of gated delay line ADTIs is fundamentally limited by the timing errors arising from the imperfections of gated delay stages including nonlinearities, thermal noise, flicker noise, supply voltage noise, skew errors, and metastability. This paper presents an analytical investigation of the impact of these imperfections on the performance of gated delay line ADTIs, backed with simulation results.