Time-Interleaving Sigma–Delta Modulator-Based Digital-to-Analog Converter With Time Multiplexing in the Analog Domain

Sigma-delta modulator based DACs are simple circuits with low accuracy requirements in their analog components. However, their signal bandwidth is limited by speed constrains. Time-Interleaving allows the designer to trade-off between complexity and speed by replacing the original architecture by a number
${M}$
of parallel paths clocked at a frequency
${M}$
times smaller. The
${M}$
digital outputs of the low-rate parallel paths are time multiplexed in a unique path at the high rate and converted to analog by means of a DAC. Unfortunately, this DAC must be also clocked at the high rate, it imposes severe restrictions on performances, and can limit the maximum frequency of operation. In this brief, the time multiplexing is performed in the analog domain by means of
${M}$
DACs clocked at the low rate. The resulting architecture is more robust against dynamic effects. The main limitation introduced by the proposed architecture comes from mismatch in the DACs’ gain, which can drastically impact performances. A new technique of dynamic elements matching is proposed here to overcome this problem. The proposed architecture benefits from the advantages of the return-to-zero pulses but, unlike a conventional DAC, maintains the robustness against clock jitter.