SiC/SiO2 interface traps effect on SiC MOSFETs Gate capacitance with biased Drain

In this paper the effects of SiC/SiO
2
interface traps on SiC MOSFETs Gate Capacitance are investigated when a positive bias is applied at the Drain terminal. The Gate capacitance arising from this configuration shows an unexpected sharp peak, exceeding the oxide capacitance, for a Gate voltage close to the threshold voltage. The properties of such peak are studied through numerical analysis. Results affirm that the peak is related to the displacement current, and its origin lies in the channel region. The so-measured Gate capacitance can allow the extraction of important interface properties, such as traps concentration at the SiC/SiO
2
interface. Also the effects of temperature on this peak are investigated through experimental and numerical analysis