Incorporating Bottom-Up Approach Into Device/Circuit Co-Design for SRAM-Based Cache Memory Applications

In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach (from device level to circuit level). The proposed device/circuit design utilizes high thermal conductivity and high permittivity of titanium dioxide (TiO2). Specifically, TiO2-based vertically stacked nanosheet field-effect transistor (NSFET) in the proposed SRAM shows the improvement of maximum lattice temperature (
${T}_{\text {MAX}}$
) from 564 to 431 K, which enables the improvement of electron mobility (
$\mu _{\text {electron}}$
) by 53.1%. In addition, the proposed device structure shows the improvement of ON-current (
${I}_{\text {on}}$
)/gate current (
${I}_{\text {gate}}$
), by 18%/1000%, compared to hafnium oxide (HfO2)-based vertically stacked NSFET. Because of this thermal/electrical performance boosting, the proposed SRAM circuit shows the enhancement of hold-signal-to-noise margin SNM (HSNM), read-SNM (RSNM), read access time (RAT), and write access time (WAT) at the same time. This thermal and electrical co-improvement indicates that the proposed device structure could enable reliable IC chip design.