A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications

A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-/spl mu/m CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 /spl times/ 1.1 mm/sup 2/. The settling time is less than 100 /spl mu/s and the phase noise is -118 dBc/Hz at 600-kHz offset.