Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS

Two-dimensional materials (2DMs) have found potential applications in many areas of electronics, such as sensing, memory systems, optoelectronics, and power. Despite an intense experimental work, the literature is lacking of accurate modeling of nonvolatile memories (NVMs) based on 2DMs. In this work, using technology CAD simulations and model calibration with experiments, we show that the experimental program/erase characteristics of floating-gate (FG) memory devices based on monolayer molybdenum disulphide can be explained by considering bandgap trap states at the dielectric–semiconductor interface. The simulation model includes a classical approach based on drift-diffusion longitudinal channel transport and on nonlocal Wentzel–Kramers–Brillouin (WKB) tunneling for transversal transport (responsible of FG charging/discharging) and for tunneling at contacts. From hysteresis and pulse programming simulations on scaled devices, we find that the long-channel programming window is still maintained at
$\sim 100$
nm and that process improvements aimed at reducing the concentration of interface traps in the semiconducting bandgap could significantly optimize memory operation.