Possible Reductions to Generate circuits from BDDs

This paper presents a systematic way to derive digital circuits from Binary Decision Diagrams (BDDs). It is well known that BDD nodes correspond to the Shannon decomposition, which can be implemented with a multiplexer. A multiplexer will result in three And-Inverter-Graph (AIG) nodes. However, simplifications may apply. This paper identifies eight different possible simplifications to the general multiplexer case. We demonstrate that applying these simplifications results in smaller AIGs derived from BDDs.