Adiabatic Logic-based STT-MRAM Design for IoT

Improving the energy-efficiency of the memory can help to meet energy constraints in the Internet of Things (IoT) devices. Recently, the Spin- Transfer- Torque based Magnetoresistive Random Access Memory (STT-MRAM) has emerged as a promising solution to design low-leakage memory for IoT devices. However, the STT mechanism results in higher dynamic power consumption. This article proposes a novel sense amplifier based on adiabatic logic for the STT-MRAM design. The proposed circuit shows an average of 68.92 % energy efficiency improvement in 8x8 STT-MRAM array in the IoT frequency range 1 MHz to 50 MHz. The SPICE simulation was carried out using 45nm CMOS technology and 40nm perpendicular magnetic anisotropy (PMA) Magnetic tunnel junctions (MTJs).