High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems

This paper proposes hardware-friendly and low-latency technique for min-sum based LDPC-decoding algorithm with flooding schedule. It enhances the data independency of LDPC decoding algorithm by mitigating dependency among the column slices. Parallel VLSI-architecture of LDPC decoder based on the proposed decoding algorithm has been presented here. Subsequently, performance analysis of such algorithm in AWGN-channel environment has shown that it delivers adequate BER of 10
⁻⁵
at 1.2 dB of channel-SNR. Furthermore, ASIC synthesis and post-layout simulation of our design are performed in 130 nm-CMOS technology-node. Thus, it occupies a core area of 6.02 mm
²
and operates at maximum clock frequency of 217 MHz. The proposed LDPC decoder is capable of delivering a high-throughput of 36 Gbps per iteration. Eventually, aforementioned results are compared with the relevant contemporary works where our design achieved 85.64% higher throughput and 41.02% better energy-efficiency in comparison with the state-of-the-art implementation.