Deriving FSM-based tests using $a,b-\text{faults}$ for Logic Circuits

Finite state machines (FSM) are widely used in testing and verification of discrete event and hybrid systems. In order to guarantee fault coverage, various fault models and formal methods are utilized ranging from classical finite state machines (FSM) to logic circuits. The main problem for deriving an FSM-based test suite is the size of an FSM for real digital circuits, and thus, test engineers prefer to randomly derive a prefix of a test sequence and later on extend it with tests for hard detectable faults of a corresponding logic circuit. Usually at the latter step test sequences detecting hard detectable stuck-at faults are considered. In this paper, we are concerned about single functional faults, namely,
$\boldsymbol{a},\boldsymbol{b}-\mathbf{faults}$
, of a system of Boolean functions of the combinational part of a sequential circuit such as deleting a variable or a cube in a SoP which represents the ON-set or the OFF-set of a corresponding Boolean function and experimentally evaluate fault coverage of a corresponding complete test suite with respect to fault coverage of tests returned by other methods. The experimental results show high fault coverage of test suites complete with respect to
$\boldsymbol{a},\boldsymbol{b}-\mathbf{faults}$
and thus, it can be recommended to utilize such a test suite instead of a complete FSM-based test suite or to extend randomly generated test sequences for detecting
$\boldsymbol{a},\boldsymbol{b}-\mathbf{faults}$
not killed with the prefix.