A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications

In the current trend, deep neural network (DNN) models that use only one type of convolution filters (mostly 3×3 convolution) are widely adopted for the hardware implementation. However, inception-type convolutional neural network (CNN) model such as GoogLeNet showed that by combining different types of convolutions like 1 × 1, 3× 3, 7×7 etc., higher level of accuracy is achievable at the lower computational cost. This paper proposes first VLSI-architecture of a hardware accelerator for such GoogLeNet CNN models and a versatile CNN accelerator-architecture that is capable of performing three different types of convolution tasks with approximately equal hardware-efficiencies. This design of hardware accelerator has been synthesized and implemented on ZYNQ-102 Ultra-Scale+ FPGA-board with 16-bit brain-float quantization that consumes only 13.7k LUTs and delivers a throughput of 13.5 GFLOPS that makes our accelerator 16.45% more hardware efficient than the state-of-the-art implementations.