Statistical measurements and Monte-Carlo simulations of DCR in SPADs

Dark Count Rate (DCR) in 3D-stacked CMOS Single-Photon Avalanche Diode (SPAD) is investigated by means of measurements and simulations at various temperatures and voltages. This study strengthens previous hypotheses on the roles of depleted regions and interfaces in DCR generation by examining device architectures. A nonradiative multiphonon-assisted trapping model (NRM) is used to calculate the carrier capture/emission rate of defect sites. Systematic comparison between measurement and Empirical Monte-Carlo (EMC) simulation, accounting for the stochastic diffusion of carriers in computation of the avalanche breakdown probability (Pt), was performed to investigate trap and avalanche positions within the device. This simulation unveils device regions contributing to different DCR dynamics by de-embedding carrier avalanche localizations. Based on this simulation methodology, the DCR statistical distribution induced by local device-to-device process variation is covered by randomly setting the defect positions and sizes within the device.