FPGA Implementation of Efficient and Low Power Test Pattern Generator

The VLSI circuits must be tested, as testing VLSI circuits presents numerous difficulties in terms of area overhead, power, and speed. One way for testing a complex architecture of VLSI Circuits is the generations of Low Power LFSR test patterns. VLSI circuits must be tested both ahead and after fabrication, as they must be tested both ahead and after fabrication (post-fabrication). For testing the VLSI design, a 32-bit Low Power-LFSR (LP-LFSR) is proposed in this paper. This 32-bit test pattern generator is built along a traditional LFSR and additional combinational network to achieve low power consumption. The LP-LFSR was designed and verified in Verilog HDL using VIVADO version 2016. The switching activity between the test vectors is reduced, resulting in low power consumption. The test pattern generation design yields a power of 16 mW. This paper describes how to improve the switching activity necessary for 32-bit test pattern generation. The experimental results show that the dynamic power of a low Power linear feedback shift register is 67.34 percent lower than that of a traditional LFSR.