A Duty Cycle Error Reduction with 1-point Calibration achieving 0.017UI in 7.2Gbps HBM3 DRAM Data Read

HBM3 PHY is a forwarded clock architecture wherein a single clock received on RDQS pad is used for sampling 42 high speed receivers present in a single DWORD during read mode. It is critical to maintain clock-to-data alignment and 50% duty cycle clock signals, across all receivers for error free operation of PHY. In this paper, we describe the method and the apparatus to partition the clock distribution network where individual pieces can be calibrated to improve the clock fidelity and alignment at 7.2Gbps. A clock amplifier with PVT tracking gain stage and multi-path calibration is proposed to keep the output clock duty cycle close to 50%. A secondary DLL generates two clocks apart by 1UI for coarse clock-to-data alignment while each sampler has a calibrated fine clock-to-data aligner to sample the incoming data at right sampling point. By partitioning the clock path in the proposed manner, we were able to maintain the clock fidelity and data alignment within ±0.017UI at the individual sampler.