Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators

Recently, an increasing number of embedded devices for neural network acceleration have adopted hardware approximations as they enable an efficient trade-off between computational resources, power consumption, and network accuracy. In this paper, we present novel approximation techniques for architectures based on bit-decomposition of the multiply and accumulate operations, especially In-memory architectures. For the target architecture, we propose seven different approximations with a high degree of freedom. We explore the design space of these approximations and evaluate their effect on architecture area and power as well as network accuracy loss. Our approximation techniques can achieve up to 26.5% power and 20% area reductions at only 1% accuracy loss.