On the reduction of output capacitance in two-level three phase PFC boost rectifier for pulsating loads

This work explores the dc-link capacitance reduction of a traditional three phase rectifier. A review of different methods for reducing the current across the dc-link capacitor, and consequently its size, is presented in this paper. In this work, the achievable capacitance reduction is explored by the action of a dual-loop control. A two-level power factor correction six-switch voltage source rectifier feeding a high demanding pulse load is analyzed. As a baseline, the output capacitor is designed from an energy storage perspective to achieve a specified maximum voltage ripple. The control design is performed in the frequency domain to get the best disturbance rejection under certain requirements and implementation constraints with the help of system time response evaluation. This work proposes a theoretical analysis that can be applied for the pursuit of converter weight reduction or other figures of merit such as volume or cost. The conclusions achieved with that theoretical study provide capacitance reduction ratios for the two-level power factor correction six-switch voltage source rectifier when implementing a classic dual-loop control algorithm.