Deterministic Dithering-Based 12-b 8-MS/s SAR ADC in 0.18-μm CMOS

This letter presents a 12-bit binary-weighted successive approximation register (SAR) ADC calibrated using self-subtractive deterministic dithering to determine the capacitor mismatch. A prototype 12-bit SAR ADC sampling at 8 MHz is realized in UMC 180-nm CMOS process and achieves an ENOB of 11.7-bits while consuming
${600~\mu }\text{W}$
of power from 1.8-V supply, thereby achieving a figure-of-merit of 22.5 fJ/conv-s and occupying only 0.13 mm2.