Hardware Realization of an Innovative Disturbance Detection Algorithm for Control Strategy of Solid-State Transfer Switch

An accurate and fast solid-state transfer switch (SSTS) has the potential to automate conventional utility network. Presently, it consumes most of the transfer time in detecting the condition for initiating the transfer process. Recent developments in the power semiconductor devices technology have reduced the switching time to the tune of nanoseconds. Hence, time consumed by the disturbance detection is significant in SSTS. IEEE Std. 1100-2005 and IEEE Std. 446-1995 require fast load transfer for SSTS. Realization of an innovative machine learning technique is implemented on three AVR microcontrollers for each of three phases. The microcontroller executes segmentation of acquired signal and calculates derivative of each segment. From each preprocessed 10-sample segment, mean absolute deviation and energy features are extracted. On the basis of feature values, support vector machine classifier with the linear kernel detects disturbance. Logical OR gate generates transfer enable signal to initiate the transfer process. Results of case studies appreciate the ability of proposed hardware to detect common disturbances in power system under different operating conditions. The hardware provides a feasible solution for SSTS with required accuracy and speed.