Effects of variations in design and process parameters on assembly process yield of area array solder interconnect packages

The objective of this paper is to investigate the effects of variations in design and process parameters on interconnect yield in assembly process of area array solder interconnect packages such as DCA, BGA, CSP and PGA. Interconnect yield loss is caused by design and process parameter variations such as solder ball height, pad size, solder mask registration, solder mask thickness, solder mask via openings, chip placement accuracy, substrate warpage, etc. It is important to control the manufacturing process so that the parameter variations are limited to certain quantities within which the desired yield is obtained. Additionally, I/O count and solderjoint size are the issues that affect interconnect yield significantly as the trend toward small size and high density continues. To control interconnect yield effectively under such unavoidable parameter variations, it is essential to understand the yield loss physics. For that purpose, cause and effect analysis was performed and theoretical interconnect yield models have been developed. The theoretical yield models provide general and explicit relationships of design and process parameters to interconnect yield. As formulas, the models may be used when a cost effective process control is to be achieved. Moreover, the closed form relationships provide an intuitive engineering analysis capturing the process physics and enabling rapid design process evaluation.