I/sub DDQ/ sensing technique for high speed IDDQ testing

In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, where the output logic level changes L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I/sub DDQ/ sensor design and external I/sub DDQ/ sensor design. It is shown experimentally that high speed I/sub DDQ/ tests can be realized by using the technique.