Analysis of the Maximum Transmission Rate of SPI Bus Between Embedded Processor and FPGA

SPI, a serial full-duplex synchronous communication bus, is typically used for data transmission between ICs. And recently, benefited from simplicity and reliability, it has gradually become a popular choice for inter-device communication, and its bandwidth design has also become a hot spot. In order to provide a foundation for the bandwidth design of the SPI bus in engineering applications, this paper analyzes the main factors affecting the transmission rate for the SPI bus communication between the embedded processor and FPGA in the single electrical domain and cross-electric domain scenarios, and establishes a calculation model of the maximum transmission rate for the SPI bus between the embedded processor and the FPGA based on the synchronization delay between asynchronous clock domain, electrical isolation delay, setup time and hold time. The SPI bus communication experiment between P2020 and Xilinx Virtex 4 FPGA shows the correctness of the proposed model.