Die-to-die alignment for lithographic processing of reconstructed wafers

In this work, we address one of the challenges of Fan-Out Wafer Level Packaging (FO-WLP), which is chip placement error, which occurs during the process of wafer reconstruction and molding. In a typical FO-WLP process, a wafer processed on a front-end tool is diced, and the dies are repositioned on a carrier with additional space created for fan-out structures. A dedicated alignment approach, which includes measurement of individual dies to adjust the settings per exposure, would result in a dramatic improvement of the overlay performance. This process further referred to as die-to-die alignment is generally known to have negative impact on throughput for IC manufacturers.The accuracy of die-to-die alignment on 200 mm wafers is evaluated experimentally in collaboration between Kulicke & Soffa and CEA LETI. The wafer layout consists of dies of different sizes (120 chips of 4 mm x 4 mm and 70 of 10 mm x 10 mm) for which intentional misalignments have been introduced with different amounts of translation (up to +/-50 micrometers) and rotation (up to +/-10 milliradians) in order to emulate typical errors found in reconstructed wafers.Alignment of the "back-end" layer with respect to existing patterns on the wafer was measured both at Kulicke & Soffa and at CEA LETI. Both measurements confirmed sub-micrometer accuracy of overlay between the structures on the reference wafer and the new layer exposed on LITEQ 500. Throughput in-line with current industrial standards was achieved. Data analysis shows that major improvements of the throughput can be achieved by optimizing the exposure process.