A Comparative Study of DPI levels on BMS IC With an On-Hand Analytical Model to Predict Resonances

When it comes to the electromagnetic interference (EMI) immunity of a Battery Management System Integrated Circuit (BMS IC), Printed Circuit Board (PCB) traces, external components and BMS impedance have a major impact. In a number of cases, electromagnetic compatibility (EMC) issues are reported at the last testing phase which can lead to design changes thus increasing cost and time to market. In this context, this work gives an insight on what some design choices on the external components, PCB traces and hot-plug (HP) protection architecture can lead to in terms of the noise coupled to the BMS IC. Moreover, an analytical model based on ladder network theory is used to predict the main noise coupling frequencies under some low-cost design choices. This model is then used in the comparison of two HP protection architectures in terms of the noise coupled onto the BMS IC.