Thermal-Aware Optimization of SoC Floorplan with Heterogenous Multi-Cores

As the performance required by System on Chip (SoC) IPs has increased, power consumption and power density have been increased. Since the SoC temperature is increasing, thermal-aware design in SoC, package, and system must meet the required target performance and reliability. Thermal-aware floorplan is an important aspect because self-heating and thermal coupling differ depending on the absolute and relative location of each IP. Moreover, it can be considered highly effective as it costs less than package and system solutions. In this paper, we demonstrate a thermal-aware floorplan optimization method considering the physical design elements of multi-core design in SoC. It also describes a method to reduce the SoC temperature comprehensively. In multi-cores, heating modules (HotSpot Area) must be separated from each other due to mutual thermal coupling. It is comfirmed by thermal simulation that the thermal resistance is much lower than that of all the attached heating modules. Also, Temperature can be reduced at the early design stage by placing the IPs appropriately in the available region across the SoC based on Cooling Zone (CZ), Keep Out Zone (KOZ), and Acceptable Zone (AZ). Simulation results indicates that the effect of thermal-aware floorplan is dominant when compared to package and system.