Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers

Two hole-current extraction methods are discussed as potential checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers on n-substrates. Both methods are unaffected by leakage currents related to defects near the junction. The one method is commonly used: the slope of the collector current in a lateral pnp Gummel plot is determined. The validity of this method is limited by series resistance and Early-voltage/punch-through effects related to depletion of the base region. The other method applies a differential measurement to determine a hole spreading current with an ideal slope. This method is not limited by depletion width variations but if the electron-to-hole current-ratio is too high, detrimental parasitic electron currents are induced.