Quick and Efficient Offset Compensation by Noise-Aware Operation of DRAM Bit Line Sense Amplifier

Power noise and threshold voltage variation of transistors in BLSA are major factors that lead to sensing errors of DRAM. This paper proposes a quick and efficient offset compensation method that is robust against transistor mismatch and power noise. Offset induced by power noise is efficiently removed by keeping the power environment unchanged while moving from the offset compensation step to the charge sharing step. Quick compensation of offset originated from transistor mismatch and power delivery network is attributed to adjustment of precharge level of bit lines for minimum initial offset. Simulation on bit line sense amplifiers in
$256\times 288$
DRAM cell array validates the analysis and confirms the superior performance of the proposed sensing method. Compared to precedent offset compensation methods, the offset generated due to power noise at the start of amplification was reduced by 16.2mV. and shortens the offset compensation time by more than 3 ns.