Charge-Trap based VMM design compensated for non-linearity through Reference Read

In this paper, we propose a highly linear Multiply-and-Accumulate function of Vector-Matrix-Multiplier (VMM) with CMOS-compatible charge-trap based memory cells. In order to eliminate the terms that cause nonlinearity of the drain current of the cell, we added one additional capacitor and three switches to implement a reference read by circuit reusing concept. As a result, the Signal-to-noise ratio (SNR) of the drain current was significantly improved, and the effective-number-of-bits (ENOB) was increased by up to x2.82 times. And, scalability to the array level was confirmed by checking that integral non-linearity (INL) was improved from 1.91LSB to 0.24LSB for 4-bit inputs in
$4\times 4$
arrays.