Optimizing Design Power Integrity using IR-Aware Placement

As the IC technology advances, voltage drop becomes increasingly significant in circuit performance. Although detecting this problem in earlier stages is helpful, only few tools are available to fix this. In this paper, the IR-drop is simulated and analyzed in 90nm technology. It utilizes the IR drop centric technology integrated in cadence tools. The experimental results shows that IR drop violations is reduce by 40% and 13% improvement of worst-case voltage degradation after the last iteration.