Deposition and characterization of low-density carbon nanotube networks on CMOS-compatible platform

Carbon nanotubes (CNTs) are one alternative building block for the new generation of electronics. One of the critical challenges is placing semiconducting CNTs as the active channel in a device configuration, while maintaining compatibility with Si-technology processes. In this work, a CMOS-compatible platform was fabricated in a first stage (as nanoscale gaps in Al electrodes on Si/SiO
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surfaces) and, in a second stage, CNTs were deposited using an inkjet printing system. By process optimization, devices containing local networks (arrays) of just a few CNTs contributing to transport can be formed. As a proof-of-concept, we also demonstrate the capability of applying an AFM-manipulation technique to modify the CNT network. This study can open a door to advanced fabrication capabilities for CNT-based transistors on a CMOS-compatible platform.