Approximate Adders for Deep Neural Network Accelerators

In this paper we propose a high-accuracy approximate carry lookahead adder that can be used with high reliability to realize DNN hardware accelerators. The Generate only Approximate adder design uses two successive group generate signals to approximate the carry. The design has an accuracy of 99.6 % while reducing the delay and PDP by 21.0 %, compared to an exact design. We have used three popular DNN architectures (LeNet, VGG16, and ResNet20) to test the suitability of the approximate design. With our design, the accuracy is degraded by a maximum of only 2.4 % for the ResNet20 architecture, whereas for the low accuracy configurations of published approximate designs, the error is as high as 90 %. Compared to high accuracy configurations, our design reduces the delay and PDP by as much as 20 % and 46 % respectively.