A 0.009mm2, 0-230mA Wide-range Load Current Output Capacitor-less Low Dropout Regulator for High Bandwidth Memory parallel IOs

Low Dropout (LDO) regulators are a part of the power management integrated circuits (PMIC) which deliver a regulated voltage supply for on-chip circuits like PLLs, DLLs, Clock distribution and critical analog circuits for parallel memory IO applications to reduce jitter. With technology scaling, the reduced voltage headroom for LDOs impact the design and the secondary effects of the MOSFET like the thermal noise, 1/f noise, gate resistance, device current leakage and output impedance become dominant. In this work, the various challenges when the output capacitor-less LDO drives a 0-230mA wide range load current with a typical dropout voltage of 125mV and having a load regulation of $73.5\mu V/mA$ are presented. The challenges become dominant when the LDO is designed on-chip in lower FinFet technology nodes. The LDO output voltage is highly dependent on the PVT variations. The focus of this work will be the impact of output load current on the device geometry, output noise and closed loop stability. The loop gain and stability of closed loop feedback is dependent on the output load, which increases the value of the output decoupling capacitance and impacts the critical KPI for LDO design - output impedance, load regulation and output voltage droop. When the load current changes from 34mA to 170mA with a rise time of 10ns, the maximum undershoot is 3mV.