Novel Circuit Architecture for configurable eDP and MIPI DPHY IO

Display interfaces are key components in present day System on Chips (SOC) as display provides maximum user experience in any product. SOCs used for smart phones, tablets or mobile segments like laptops use Embedded Display Port (eDP) interface or MIPI Display Serial Interface (DSI) for driving display panels. Most SOCs integrate both eDP PHY (Physical layer) and MIPI DPHY to enable SOC reusability across smallest display (MIPI DSI) application to high resolution display (eDP) use cases. As a result, one PHY is unused in most SOC based on application. This paper describes Input output (IO) Architecture & circuit topology to integrate eDP and MIPI DPHY. The paper also describes circuit Architecture to achieve integrate PHY using thingate devices to enable design in sub nm (nanometer) process technology, this paper explains implementation and post silicon results eDP-MIPI Combophy.