An Efficient Dual Stage Compressor for High Speed VLSI Applications

Approximation can be used to reduce the overhead on compute units of a processor, allowing it to achieve high performance and execution efficiency. The speed of operation, which is inversely proportional to the system's latency, necessitates massive parallel processes that consume a lot of hardware and energy. Relaxing the accuracy and dependability of the system might result in energy and area efficient solutions. Approximate computing has emerged as a viable method for maintaining the balance between latency, area, and power. A typical operation in approximation computing systems for high speed and low power computing is approximate application. These applications provide tremendous performance at the expense of precision. Furthermore, such methods minimise system architectural complexity, latency, and power consumption. An approximate 4:2 compressor can be used to create power-efficient circuits for approximation multiplication. This paper proposes a novel design that uses a modification of a previous approximate 4:2 compressor design and adds an error recovery module, delay and power with comparable accuracy when compared with the existing architecture. Even with the extra error recovery module, the suggested design is more accurate, uses less hardware, and consumes less power than the previously proposed approximation multiplier design based on 4:2 compressor. These designs are made with 130nm CMOS technology, and their efficiency has been thoroughly tested and predicted on scales of power, delay and Power Delay Product (PDP). An unique 4:2 compressor architecture with excellent speed, area efficiency, and low power is suggested. The proposed compressors are utilized to implement in multipliers. The study will also be expanded to include high-speed applications.