Performance evaluation of SRAM cell using FinFET

As CMOS devices near the nanometer regime, scaling them down has a number of repercussions, such as short channel effects and process fluctuations, which degrade the device's reliability and performance. FinFET is one of the promising ones for overcoming this problem, according to researchers, because it has better channel management and lower overall capacitance, the 6T Static Random Access Memory (SRAM) circuit design will perform better. This research study evaluates 6T and 9T SRAM cells created with CMOS and FinFET by utilizing 22nm technology and further these SRAM cells are compared based on numerous performance characteristics such as write delay, read delay, static power and static noise margin (SNM). The Predictive Technology Models (PTM) files are used to simulate the 22nm CMOS and FinFET based SRAM cells which are developed by Arizona State University in the Cadence Virtuoso tool.